View ADP5023_4088314.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual 3 mhz, 800 ma buck regulators with one 300 ma ldo data sheet ADP5023 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011-2012 analog devices, inc. all rights reserved. features main input voltage range: 2.3 v to 5.5 v two 800 ma buck regulators and one 300 ma ldo 24-lead, 4 mm 4 mm lfcsp package regulator accuracy: 3% factory programmable or external adjustable voutx 3 mhz buck operation with forced pwm and auto pwm/psm modes buck1/buck2: output voltage range from 0.8 v to 3.8 v ldo: output voltage range from 0.8 v to 5.2 v ldo: input supply voltage from 1.7 v to 5.5 v ldo: high psrr and low output noise applications power for processors, asic, fpgas, and rf chipsets portable instrumentation and medical devices space constrained devices general description the ADP5023 combines two high performance buck regulators and one low dropout (ldo) regulator in a small, 24-lead 4 mm 4 mm lfcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. when the mode pin is set high, the buck regulators operate in forced pwm mode. when the mode pin is set low, the buck regulators operate in pwm mode when the load current is above a predefined threshold. when the load current falls below a predefined threshold, the regulator operates in power save mode (psm) improving the light-load efficiency. the two bucks operate out of phase to reduce the input capaci- tor requirement. the low quiescent current, low dropout voltage, and wide input voltage range of the ADP5023 ldo extends the battery life of portable devices. the ADP5023 ldo maintains power supply rejection greater than 60 db for frequencies as high as 10 khz while operating with a low headroom voltage. regulators in the ADP5023 are activated though dedicated enable pins. the default output voltages can be externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version. typical application circuit vin1 vin3 en1 pwm psm/pwm 2.3v to 5.5v sw1 fb1 r2 r1 vout1 pgnd1 mode c5 10f v out1 at 800ma v out2 at 800ma v out3 at 300ma l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f avin c filt 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v to 5.5v on off on off en3 ldo ADP5023 housekeeping sw2 fb2 r4 r3 vout2 pgnd2 c6 10f l2 1h fb3 r6 r5 vout3 c7 1f 09889-001 figure 1.
ADP5023 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical application circuit ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? general specifications ................................................................. 3 ? buck1 and buck2 specifications ........................................... 4 ? ldo specifications ...................................................................... 5 ? input and output capacitor, recommended specifications .. 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? power dissipation and thermal considerations ....................... 15 ? buck regulator power dissipation .......................................... 15 ? junction temperature ................................................................ 16 ? theory of operation ...................................................................... 17 ? power management unit ........................................................... 17 ? buck1 and buck2 .................................................................. 19 ? ldo .............................................................................................. 20 ? applications information .............................................................. 21 ? buck external component selection ....................................... 21 ? ldo external component selection ...................................... 23 ? pcb layout guidelines .................................................................. 24 ? typical application schematics .................................................... 25 ? bill of materials ............................................................................... 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 1/12rev. 0 to rev. a changes to features section............................................................ 1 changes to table 2 ............................................................................ 4 changes to table 3 and table 4 ....................................................... 5 changes to table 5 ............................................................................ 6 changes to table 7 ............................................................................ 7 changes to figure 34 ...................................................................... 13 changes to buck regulator power dissipation section ............ 15 changes to undervoltage lockout section ................................. 18 changes to ldo section and figure 48 ...................................... 20 changes to table 9 .......................................................................... 22 changes to figure 52 ...................................................................... 25 changes to ordering guide .......................................................... 27 8/11revision 0: initial version
data sheet ADP5023 rev. a | page 3 of 28 specifications general specifications v avin = v in1 = v in2 = 2.3 v to 5.5 v; v in3 = 1.7 v to 5.5 v; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit input voltage range v avin , v in1 , v in2 2.3 5.5 v thermal shutdown threshold ts sd t j rising 150 c hysteresis ts sd - hys 20 c start - up time 1 buck1, ldo t start1 250 s buck2 t start2 300 s en1, en2, en3, mode inputs input logic high v ih 1.1 v input logic low v il 0.4 v input leakage current v i- leakage 0.05 1 a input current all channels enabled i stby - nosw no load, no buck switching 108 1 7 5 a all channels disabled i shutdown t j = ?40c to +85c 0.3 1 a vin1 undervoltage lockout high uvlo input voltage rising uvlo vin1rise 3.9 v high uvlo input voltage falling uvlo v in1 fal l 3.1 v low uvlo input voltage rising uvlo vin1rise 2.275 v low uvlo input voltage falling uvlo vin1 fal l 1.95 v 1 start - up time is defined as the time from en1 = en2 = en3 from 0 v to v avin to vout1, vout2, and vout3 reaching 90% of their nominal level. start - up times are shorter for individual channels if another channel is already enabled. see the typical performance characteristics section for more information .
ADP5023 data sheet rev. a | page 4 of 28 b uck 1 and b uck 2 specifications v avin = v in1 = v in2 = 2.3 v to 5.5 v; t j = ? 40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 2 . par ameter symbol test conditions/comments min typ max unit output characteristics output voltage accuracy v out1 /v out1 , v out2 /v out2 pwm mode ; i load1 = i load2 = 0 ma to 800 ma ? 3 +3 % line regulation (v out1 /v out1 )/v in1 , (v out2 /v out2 )/v in2 pwm mo de ? 0.05 %/v load regulation ( v out1 /v out1 )/ i out1 , ( v out2 /v out2 )/ i out2 pwm mode ; i load = 0 ma to 800 ma ? 0.1 %/a voltage feedback v fb1 , v fb2 models with adjustable outputs 0.485 0.5 0.515 v operating supply current mode = ground buck1 only i in i load1 = 0 ma, device not switching, all other channels disabled 44 a buck2 only i in i load2 = 0 ma, device not switching, all other channels disabled 55 a buck1 and buck2 i in i load1 = i load2 = 0 ma, device not switching, ldo channels disabled 67 a psm current threshold i psm psm to pwm operation 100 ma sw characteristics sw on resistance r n fet v in1 = v in2 = 3.6 v 155 240 m r p fet v in1 = v in2 = 3.6 v 205 310 m r n fet v in1 = v in2 = 5.5 v 1 37 204 m r p fet v in1 = v in2 = 5.5 v 1 62 243 m current limit i limit1 , i limit2 pfet switch peak current limit 1600 1950 2300 ma active pull - down r pdwn - b channel disabled 75 oscillator frequency f sw 2.5 3.0 3.5 mhz 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc).
data sheet ADP5023 rev. a | page 5 of 28 ldo specifications v in3 = (v out3 + 0.5 v) or 1.7 v (whichever is gr eater) to 5.5 v; c in = c out = 1 f; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 3 . parameter symbol test conditions/comments min typ max unit i nput voltage range v in3 1.7 5.5 v operating supply current bias current per ldo 2 i vin3bias i out3 = 0 a 10 30 a i out3 = 10 ma 60 100 a i out3 = 300 ma 165 245 a total system input current i in includes all current into avin, vin1, vin2 , and vin 3 ldo only i out3 = 0 a , all other channels disabled 53 a output characteristics output voltage accuracy v out3 /v out3 100 a < i out3 < 300 ma ? 3 +3 % line regulation (v out3 /v out3 )/v in3 i out3 = 1 ma ? 0.03 +0.03 % / v load regulation 3 (v out3 /v out3 )/i out3 i out3 = 1 ma to 300 ma 0.001 0.003 %/ma voltage feedback v fb3 0.485 0.5 0.515 v dropout voltage 4 v dropout v out3 = 5.2 v, i out3 = 300 ma 50 mv v out3 = 3.3 v, i out3 = 300 ma 75 140 mv v out3 = 2.5 v, i out3 = 300 ma 100 mv v out3 = 1.8 v, i out3 = 300 ma 180 mv current - limit threshold 5 i limit3 335 600 ma active pull - down r pdwn - l channel d isabled 600 output noise regulator ldo noise ldo 10 hz to 100 khz, v in3 = 5 v, v out3 = 2.8 v 100 v rms power supply rejection ratio psrr regulator ldo 10 khz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 60 db 100 khz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 62 db 1 mhz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 63 db 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 this is the input current into vin3, which is not delivered to the output load. 3 based on an endpoint calculation using 1 ma and 3 00 ma loads. 4 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this applies only to ou tput voltages above 1.7 v. 5 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for exampl e, the current limit for a 3.0 v output voltage is defined as the current that causes the outp ut voltage to drop to 90% of 3.0 v, or 2.7 v. input and output cap acitor, recommended specifications t a = ?40c to +125c, unless otherwise specified. table 4 . parameter symbol min typ max unit nominal input and output capacit or ratings buck1, buck2 input capacitor ratings c min1 , c min2 4.7 40 f buck1, buck2 output capacitor ratings c min1 , c min2 10 40 f ldo 1 input and output capacitor ratings c min3 , c min4 1. 0 f capacitor e sr r esr 0.001 1 1 the minimum input and output capacitance should be greater than 0. 7 0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r - and x5r - type capacitors are recommended; y5v and z5u capacitors are not recommended for use because of their poor temperature and dc bias characteristics .
ADP5023 data sheet rev. a | page 6 of 28 absolute maximum rat ings table 5 . parameter rating avin to agnd ? 0.3 v to + 6 v vin1, vin2 to avin ? 0.3 v to +0.3 v pgnd1, pgnd2 to agnd ? 0.3 v to +0.3 v vin3, vout1, vout2, fb1, fb2, fb3, en1, en2, en3, mode to a g nd ? 0. 3 v to ( a vin + 0.3 v) vout3 to agnd ? 0.3 v to (vin 3 + 0.3 v) sw1 to pgnd1 ? 0.3 v to (vin1 + 0.3 v) sw2 to pgnd2 ? 0.3 v to (vin 2 + 0.3 v) storage temperature range ? 65c to +150c operating junction temperature range ? 40c to +125c soldering conditio ns jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operatio nal section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for detailed information on power dissipation, see the power dissi pation and thermal considerations section. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 24- lead, 0.5 mm pitch lfcsp 35 3 c/w esd caution
data sheet ADP5023 rev. a | page 7 of 28 pin configuration an d function descripti ons 09889-002 2 1 3 4 5 6 18 17 16 15 14 13 nc pgnd2 notes 1. nc = no connec t . do not connect t o this pin. 2. it is recommended th a t the exposed p ad be soldered t o the ground plane. sw2 vin2 gnd gnd mode pgnd1 sw1 vin1 a vin agnd 8 9 10 1 1 7 fb2 vout2 vout1 fb1 12 en1 en2 20 19 21 vout3 fb3 vin3 22 en3 23 gnd 24 gnd ADP5023 t op view (not to scale) figure 2 . pin configuration view from top of die table 7 . pin function descriptions p in no. mnemonic description 1 agnd analog ground. 2 agnd analog ground. 3 vin2 buck2 input supply (2.3 v to 5.5 v) . connect vin2 to vin1 and avin . 4 sw2 buck2 switching node . 5 pgnd2 dedicated power ground for buck2 . 6 nc no connect. leave this pin unconnected . 7 en2 buck 2 enable pin. high level turn s on this regulator, and low level turn s it off. 8 fb2 buck2 feedback input. for device models with a djustable output voltage, connect this pin to the middle of the buck2 resistor divider . for device mo dels with fixed output voltage, leave this pin unconnected. 9 vout2 buck 2 output voltage sensing input. connect vout2 to the top of the capacitor on vout2. 10 vout1 buck 1 output voltage sensing input. connect vout1 to the top of the capacitor on vout1. 11 fb1 buck 1 feedback input. for device models with a djustable output voltage, connect this pin to the middle of the buck1 resistor divider . for device models with fixed output voltage, connect this pin to the top of the capacitor on vout3 . 12 en1 buck 1 enable pin. high level turn s on this regulator, and low level turn s it off. 13 mode buck 1 / buck 2 operating mode . mode = high : f orced pwm operation. mode = low : a uto pwm/psm o peration. 14 pgnd1 dedicated power ground for buck1 . 15 sw1 buck 1 switching nod e 16 vin1 buck 1 input supply (2.3 v to 5.5 v ). connect vin1 to vin2 and avin . 17 avin analog input supply (2.3 v to 5.5 v) . connect avin to vin1 and vin2 . 18 agnd analog ground . 19 fb3 ldo feedback input. for device models with a djustable output voltag e, connect this pin to the middle of the ldo resistor divider . for device models with fixed output voltage, leave this pin unconnected. 20 vout3 ldo output voltage . 21 vin3 ldo input supply (1.7 v to 5.5 v ) . 22 en3 ldo enable pin. high level turn s on th is regulator, and low level turn s it off. 23 agnd analog ground. 24 agnd analog ground. epad (ep) exposed pad. it is recommended that the exposed pad be soldered to the ground plane.
ADP5023 data sheet rev. a | page 8 of 28 typical performance characteristics v in1 = v in2 = v in3 = 3 .6 v, t a = 25c , unless otherwise noted. 0 20 40 60 80 100 120 140 2.3 2.8 3.3 3.8 4.3 4.8 5.3 input vo lt age (v) quiescent current (a) 09889-139 figure 3 . system quiescent current vs. input voltage, v out1 = 3.3 v, v out2 = 1.8 v, v out3 = 1.2 v, v out4 = 3.3 v, all channels unloaded 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 1 1.20% ch2 50.0m a ? ch3 5.00v sw iout vout en 09889-021 figure 4. b uck 1 startup, v out 1 = 1. 8 v, i out1 = 5 ma 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 1 1.20% ch2 50.0m a ? ch3 5.00v sw iout vout en 09889-020 figure 5 . buck2 startup, v out2 = 3. 3 v, i out2 = 10 ma 3.35 3.33 3.31 3.29 3.27 3.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out (v) v in = 4.2 v , +25c v in = 4.2 v , +85c v in = 4.2 v , ?40c 09889-058 figure 6 . buck1 load regulation across temperature, v out1 = 3.3 v, auto mode 1.864 1.764 1.784 1.804 1.824 1.844 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out (v) v in = 3.6 v , +25c v in = 3.6 v , +85c v in = 3.6 v , ?40c 09889-057 figure 7 . buc k2 load regulation across temperature, v out2 = 1.8 v, auto mode 0.799 0.789 0.791 0.793 0.795 0.797 0.798 0.790 0.792 0.794 0.796 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out (v) v in = 3.6 v , +25c v in = 3.6 v , +85c v in = 3.6 v , ?40c 09889-054 figure 8 . buck1 load regulation across input voltage, v out1 = 3.3 v, pwm mode
data sheet ADP5023 rev. a | page 9 of 28 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficienc y (%) v in = 3.9v v in = 4.2v v in = 5.5v 09889-038 figure 9 . buck1 efficiency vs. load current, across i nput voltage, v out1 = 3.3 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) v in = 3.9v v in = 4.2v v in = 5.5v 09889-039 figure 10 . buck1 efficiency vs. load current, across input voltage, v out1 = 3.3 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09889-036 figure 11 . buck2 efficiency vs. load current, across input volta ge, v out2 = 1.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09889-035 figure 12 . buck2 efficiency vs. load current, across input voltage, v out2 = 1.8 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09889-034 figure 13 . buck1 efficiency vs. load current, across input voltage, v out1 = 0.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09889-035 figure 14 . buck1 efficiency vs. load current, across input voltage, v out1 = 0.8 v, pwm mode
ADP5023 data sheet rev. a | page 10 of 28 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) +25c +85c ?40c 09889-062 figure 15 . buck1 efficiency vs. load current, across temperature, v in = 3.9 v, v ou t1 = 3.3 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) +25c +85c ?40c 09889-063 figure 16 . buck2 efficiency vs. load current, across temperature, v out2 = 1.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficienc y (%) +25c +85c ?40c 09889-200 figure 17 . buck 1 efficiency vs. load current, across temperature, v out 1 = 0.8 v, au to mode 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 0 1.2 1.0 0.8 0.6 0.4 0.2 i out (a) frequenc y (mhz) t a = +25c t a = ?40c t a = +85c 09889-040 figure 18 . buck2 switching frequency vs. output current, across temperature, v out2 = 1.8 v, pwm mode 2 4 t 1 ch1 50.0mv m 4.00s a ch2 240ma t 28.40% ch2 500m a ? ch4 2.00v i sw vout sw 09889-025 figure 19 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, auto mode 2 4 t 1 ch1 50.0mv m 4.00s a ch2 220ma t 28.40% ch2 500m a ? ch4 2.00v i sw vout sw 09889-024 figure 20 . typical waveforms, v out2 = 1.8 v, i out2 = 30 ma, auto mode
data sheet ADP5023 rev. a | page 11 of 28 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% ch2 500m a ? ch4 2.00v i sw vout sw 09889-027 figure 21 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, pwm mode 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% ch2 500m a ? ch4 2.00v i sw vout sw 09889-026 figure 22 . typical waveforms, v out2 = 1.8 v, i ou t2 = 30 ma, pwm mode ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v 1 3 t 30.40% t vout vin sw 09889- 1 12 figure 23 . b uck 1 response to line transient, v in = 4.5 v to 5.0 v, v out1 = 3.3 v, pwm mode 1 4 t 3 ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v t 30.40% vout vin sw 09889-013 figure 24 . buck2 response to line transient, v in = 4.5 v to 5.0 v, v out2 = 1.8 v, p wm mode 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 356ma t 60.000s ch2 50.0m a ? vout i out sw 09889-016 figure 25 . buck1 response to load transient, i out1 = 1 ma to 50 ma, v out1 = 3.3 v, auto mode 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 379ma t 22.20% ch2 50.0m a ? vout i out sw 09889-015 figure 26 . buck2 response to load transient, i out2 = 1 ma to 50 ma, v out2 = 1.8 v, auto mode
ADP5023 data sheet rev. a | page 12 of 28 4 2 t 1 ch1 50.0mv ch4 5.00v m 20.0s a ch2 408ma t 20.40% ch2 200m a ? vout i out sw 09889-017 figure 27 . buck1 response to load transient, i out1 = 20 ma to 180 ma, v out1 = 3.3 v, auto mode 4 2 t 1 ch1 100mv ch4 5.00v m 20.0s a ch2 88.0ma t 19.20% ch2 200m a ? vout i out sw 09889-018 figure 28 . buck2 response to load transient, i out2 = 20 ma to 180 ma, v out2 = 1.8 v, auto mode 4 1 3 t 2 ch1 5.00v ch4 5.00v m 400ns a ch4 1.90v t 50.00% ch2 5.00v ch3 5.00v vout1 vout2 sw1 sw2 09889-066 fi gure 29 . vout and sw waveforms for buck1 and buck2 in pwm mode showing out - of - phase operation 2 3 t 1 ch1 2.00v m 40.0s a ch3 2.2v t 1 1.20% ch2 50.0m a ? ch3 5.00v vout en i in 09889-022 figure 30 . ldo startup, v out3 = 3.0 v, i out3 = 5 ma 2.820 2.780 2.785 2.790 2.795 2.800 2.805 2.810 2.815 0 0.05 0.10 0.15 0.20 0.25 0.30 i out (a) v out c (v) v in = 3.3v v in = 4.5v v in = 5.0v v in = 5.5v 09889-046 figure 31 . ldo load regula tion across input voltage, v out3 = 2.8 v 0 50 100 150 200 250 300 350 400 2.3 2.8 3.3 3.8 4.3 4.8 5.3 rd s on (m?) input vo l t age (v) 09703-037 +25c +125c ?40c figure 32 . nmos rds on vs. input voltage across temperature
data sheet ADP5023 rev. a | page 13 of 28 2.3 2.8 3.3 3.8 4.3 4.8 5.3 rd s on (m?) input vo l t age (v) 09703-038 +125c +25c ?40c 0 50 100 150 200 250 figure 33 . pmos rds on vs. input voltage across temperature 3.45 3.15 3.20 3.25 3.30 3.35 3.40 0 0.30 0.25 0.20 0.15 0.10 0.05 i out (a) v out (v) v in = 4.2 v , +25c v in = 4.2 v , +85c v in = 4.2 v , ?40c 09889-049 figure 34 . ldo load regulation across temperature, v in3 = 4.2 v, v out3 = 3.3 v 3.0 2.5 2.0 1.5 1.0 0.5 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) v out (v) i out = 300m a i out = 150m a i out = 100m a i out = 10m a i out = 1m a i out = 100 a 09889-045 figure 35 . ldo line regulation across output load, v out3 = 2.8 v 0 0.05 0.10 0.15 0.20 0.25 ground current (a) i out (a) 0 5 10 15 20 25 30 35 40 45 50 09889-136 figure 36 . ldo ground current vs. output load, v in3 = 3.3 v, v out3 = 2.8 v 2 t 1 ch1 100mv m 40.0s a ch2 52.0ma t 19.20% ch2 100m a ? vout i out 09889-019 figure 37 . ldo response to load transient, i out3 = 1 ma to 80 ma, v out3 = 2.8 v 2 3 t 1 ch1 20.0mv ch3 1.00v m 100s a ch3 4.80v t 28.40% vout vin 09889-014 figure 38 . ldo response to line transient, v in = 4.5 v to 5.5 v, v out3 = 2.8 v
ADP5023 data sheet rev. a | page 14 of 28 60 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i out (ma) rms noise (v) v in = 3.3v v in = 5v 09889-047 figure 39 . ldo output noise vs. load current, across input voltage, v out3 = 2.8 v 60 65 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i out (ma) rms noise (v) 09889-048 v in = 3.3v v in = 5v figure 40 . ldo output noise vs. load current, across input voltage, v out3 = 3.0 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 100 a 1m a 10m a 50m a 100m a 150m a 09889-050 figure 41 . ldo psrr acros s output load, v in3 = 3.3 v, v out3 = 2.8 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 100 a 1m a 10m a 50m a 100m a 150m a 09889-051 figure 42 . ldo psrr across output load, v in3 = 3.3 v, v out3 = 3.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 100 a 1m a 10m a 50m a 100m a 150m a 09889-053 figure 43 . ldo psrr across output load, v in3 = 5.0 v, v out3 = 2.8 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 100 a 1m a 10m a 50m a 100m a 150m a 09889-052 figure 44 . ldo psrr across output load, v in3 = 5.0 v, v out3 = 3.0 v
data sheet ADP5023 rev. a | page 15 of 28 power dissipation and thermal consideratio ns the ADP5023 is a highly efficient pmu, and , in most cases , the power dissipate d i n the device is not a concern. however, if the device operates at high ambient temperatures and maxi - mum loading condition, the junction temperature can reach the maximum allowable operating limit (125c). when the temperature exceeds 150c, the ADP5023 turns off all the regulators, all owing the device to cool down. when the die temperature falls below 13 0 c, the ADP5023 resumes normal operation. this section pr ovides guidelines to calculate the power dissi - pated in the device and en sure that the ADP5023 operates below the maximum allowable junction temperature. the efficiency for each regulator on the ADP5023 is given by 100% = in out p p (1) where: is the e fficiency . p in is the input power. p out is the output power. power loss is given by p loss = p in ? p out (2a) or p loss = p out (1? )/ (2b) power dissipat ion can be calculated in several ways. the most intuitive and practical is to measure the power dissipated at the input and all the outputs. perform t he measurements at the worst - case conditions (voltages, currents , and temperature). the difference between input and output power is dissipated in the device and the inductor. use equation 4 to derive the power lost in the inductor, and from this use equation 3 to calculate the power dissipation in the ADP5023 buck converter. a second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on the ldo can be calculated using equation 12. when the buck eff iciency is known, use equation 2b to derive the to tal power lost in the buck regulator and inductor, use equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using equation 3. add the power dissipated in the buck and in the ldo to find the tot al dissipated power. note that the buck efficiency curves are typical values and may not be provided for all possible combinations of v in , v out , and i out . to account for these variations , it is necessary to include a safety margin when calculating the powe r dissipated in the buck. a third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provid ed by equation 8 to equation 11 and the losses in the ldo provided by equation 12. buck regulator p ower d issi pation the power loss of the buck regulator is approximated by p loss = p dbuck + p l (3) where: p dbuck i s the power dissipation on one of the ADP5023 buck regulator s. p l is the inductor power losses. the inducto r losses are external to the device and do not have any effect on the die temperature. the inductor losses are estimated (without core losses) by p l i out1(rms) 2 dcr l (4) where: dcr l is the inductor series resistance. i out1(rms) is the rms load current of the buck regulator. 12 + 1 ) ( 1 r i i out1 rms out = (5) where r is the normalized inductor ripple current r = v out1 (1 ? d )/( i out1 l f sw ) (6) where: l is the inductance. f sw is the switching frequency. d is the duty cycle. d = v out1 / v in1 (7) ADP5023 buck regulator power dissipation, p dbuck , includes the power switch conductive losses, the switch losses, and the transi - tion losses of each channel. there are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is . equation 8 captures the calculation that must be made to estimat e the power dissipation in the buck regulator. p dbuck = p cond + p sw + p tran (8) the power switch conductive losses are due to the output current, i out1 , flowing through the p - mosfet and the n - mosfet power switches that have internal resistance, rds on - p and rds on - n . the amount of conductive power loss is found by p cond = [ rds on - p d + rds on - n (1 ? d )] i out1 2 (9) where rds on - p is approximately 0.2 ?, and rds on - n is approxi - mately 0.16 ? at 125c junction temperature and vin 1 = vin2 = 3.6 v. at vin 1 = vin2 = 2.3 v, these values change to 0.31 ? and 0.21 ?, respectively, and at vin1 = vin2 = 5.5 v, the values are 0.16 ? and 0.14 ? , respectively .
ADP5023 data sheet rev. a | page 16 of 28 switching losses are associated with the current drawn by the driver t o turn on and turn off the power devices at the switching frequency. the amount of switching power loss is given by p sw = ( c gate - p + c gate - n ) v in1 2 f sw (10) where: c gate - p is the p - mosfet gate capacitance. c gate - n is the n - mosfet gate capacitance. for the ADP5023 , the total of ( c gate - p + c gate - n ) is approximately 150 pf. the transit ion losses occur because the p - channel power mosfet cannot be turned on or off instantaneously, and the sw node takes some time to slew from near ground to near v out1 (and from v out1 to ground). the amount of transition loss is calculated by p tran = v in1 i out1 ( t rise + t fall ) f sw (11) where t rise and t fall are the rise time and the fall time of the switching node, sw. for the ADP5023 , the rise and fall times of sw are in the order of 5 ns. if the preceding equations and parameters are used for estimat - ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. the converter performance also depends on the choice of passive components and board layout ; therefore, a sufficient safety margin should be included in the estimate. ldo regulator power dissipation the power loss of a ldo regulator is given by p dldo = [( v in ? v out ) i load ] + ( v in i gnd ) (12) where: i load is the load current of the ldo regulator. v in and v out are input and output voltages of the ldo, respectively. i gnd is the ground current of the ldo regulator. power dissipation due to the ground current is small and it can be ignored. junction t emperature in cases where the board temperature t a is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula t j = t a + ( p d ja ) (14) the typical ja value for the 24 - lead, 4 mm 4 mm lfcsp is 35 c/w (see table 6 ). a very important factor to consider is that ja is based on 4 - layer , 4 in 3 in , 2.5 oz copper, as per jedec standard, and real applications may use different sizes and layers. it is important to maximize t he copper used to remove the heat from the device . copper exposed to air dissipate s heat better than co pper used in the inner layers. the exposed pad should be connected to the ground plane with several vias . if the case temperature can be measured , the ju nction temperature is calculated by t j = t c + ( p d jc ) (15) where t c is the case temperature and jc is the junction - to - case thermal resistance provided in table 6 . when designing an application for a particular ambient temperature range, calculate the expected ADP5023 power dissipation (p d ) due to the losses of all channels by using equation 8 to equation 13. from this power calculation, the junction temperature, t j , can be estimated using equation 14. the reliable ope ration of the converter and the two ldo regulators can be achieved only if the estimated die junction temperature of the ADP5023 (equation 14) is less than 125c. reliability and mean time between failures (mtb f) is highly affected by increas - ing the junction temperature. additional information about product reliability can be found from the adi reliability handbook , which can be found at www.analog.com/r eliability_handbook . the total power dissipation in the ADP5023 simplifies to p d = p dbuck 1 + p dbuck 2 + p dldo (13)
data sheet ADP5023 rev. a | page 17 of 28 theory of operation enable and mode contro l ldo contro l ldo unde r volt age lock out soft s t art pwm/ psm contro l buck2 driver and antishoot through soft s t art pwm/ psm contro l buck1 driver and antishoot through oscill a t or therma l shutdown system unde r volt age lockout pwm com p gm error am p gm error am p psm com p psm com p low current i limit pwm com p low current i limit r1 r2 ADP5023 vout1 fb1 fb2 vout2 vin1 a vin sw1 pgnd1 en1 en2 enbk1 enbk2 enldo en3 vdd a vin3 agnd fb3 vout3 pgnd2 mode sw2 vin2 enldo 600? enbk2 75? enbk1 75? b a y se l opmode mode2 09889-003 figure 45 . functional block diagram p ower m an a g e ment u nit the ADP5023 is a micropower management unit ( micro pmu ) combin in g two step - down ( buck ) dc - to - dc converte rs and one low dropout linear regulator (ldo). the high switch ing frequency and tiny 24 - l ead lf csp package allow s a small power management solution. to combine these high performance regulator s into the micro pmu , there is a system controller allowing them to operate together. the buck regulator s can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the buck switching frequency is always constant and does not change with the load current. if the mode pin is at a logic low level , the switching regulators operate in auto pwm/psm mode. in this mode, the regulat ors operate at fixed pwm frequency when the load current is above the psm current threshold. when the load current falls below the psm current threshold , the regulator in question enters psm, where the switching occurs in bursts . t he burst repetition rate is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses. the auto pwm/psm mode transition is controlled independently for each buck regulator. the two bucks operate synchroniz ed to each other. the ADP5023 has individual enable pins (e n 1 to en3 ) control - ling the activation of each regulator . the regulators are activated by a logic level high app lied to the respective en pin. en1 cont rols buck1 , en2 controls buck2 , and en3 controls ldo . regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values ( see the ordering guide section ) . when a regulator is turned on, the output voltage ramp rate is controlled though a soft start circuit to avoid a large inrush current due to the charging of the output capacitors. thermal protection in the event that the junction temperature rises abov e 150c, the thermal shutdown circuit turns off all the regulators . extreme junction temperatures can be the result of high current
ADP5023 data sheet rev. a | page 18 of 28 operation, poor circuit board design, or high ambient temperature. a 20c hysteresis is included so that when thermal shutdo wn occurs, the regulators do not return to operation until the on - chip temperature drops below 130c. when coming out of thermal shutdown, all regulators re start with soft - start control . undervoltage lockout to protect against battery discharge, undervolta ge lockout (uvlo) circuitry is integrated i n to the system . if t he input voltage on vin1 drops below a typical 2.15 v uvlo threshold, all channels shut down . i n the b uck channel s, both the power switch and the synchronous rectifier turn off. when the voltag e on vin1 rises above the uvlo threshold, the part is enabled once more . alternatively, the user can select device models with a uvlo set at a higher level, suitable for usb applications . for these models , the device reaches the turn - off threshold when the input supply drops to 3. 65 v typical . in case of a thermal or uvlo even t , the active pull - down s (if factory enabled) are enabled to discharge the output capacitors quickly . the pull - down resistors remain engaged until the the rmal fault event is no longer present , or the input supply voltage falls below the v por voltage level. the typical value of v por is approx - imately 1 v . enable/ shutdown the ADP5023 has an individual control pin for each regulator. a logic le vel high applied to the enx pin activate s a regulator, whereas a logic level low turns off a regulator. figure 46 shows the regulator activation timings for the ADP5023 when all enable pins are connected to av in . a lso show n is the active pull - down activation. a vin vout3 vout1 vuvlo vout2 vpor buck2 pull-down buck1, ldo1 pull-downs 50s (min) 30s (min) 50s (min) 30s (min) 09889-148 figure 46 . regulator sequencing on ADP5023 ( en1 = en2 = en3 = v avin )
data sheet ADP5023 rev. a | page 19 of 28 b uck 1 and b uck 2 th e buck uses a fixed frequency and high speed current mode architecture. the buck operates with an input voltage of 2.3 v to 5.5 v. the b uck output voltage is set th r ough external resistor divider s, shown in figure 47 for buck1 . the output voltage can optionally be factory programmed to default values as indicated in the ordering guide section. in this event , r1 and r2 are not needed , and fb1 can be left unconnected. in all cases, vout1 must be connected to the output capacitor. fb1 is 0. 5 v. buck pgnd fb1 sw1 r1 r2 vout1 vout1 vin1 l1 1h c5 10f v out1 = v fb1 + 1 r1 r2 09889-008 figure 47 . b uck1 external output voltage setting control scheme the bucks operate with a fixed frequency, current mode pwm control architecture at medium to h igh loads for high efficiency, but shift to a power save mode (psm) control scheme at light loads to lower the regulation power losses. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted and regulates the outp ut voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. dur ing part of this time, the converter is able to stop switching and enters an idle mode, which improves conversi on efficiency. pwm mode in pwm mode, the bucks operate at a fixed frequency of 3 mhz set by an internal oscillator. at the start of each oscillator cycle, the p fet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the p fet switch and turns on the n fet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. t he synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshold. power save mode (psm) the bucks smoothly transition to psm operation when the load current decreases below the psm curr ent threshold. when either of the bucks enter s psm , an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacitor discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the inductor to make the output volt age rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold. the ADP5023 has a dedicated mode pin controlli ng the psm and pwm operation. a high logi c level applied to the mode pin f orce s both b uck s to operate in pwm mode . a logic level low set s the bucks to operate in auto psm/pwm. psm current threshold the psm current threshold is set to 10 0 ma . the bucks employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to and exit from the psm . the psm current threshold is optimized for ex cellent efficiency over all load currents. oscillator/ phasing of inductor switching the ADP5023 ensure s that both bucks operate at the same switching frequency when both bucks are in pwm mode. additionally, the ADP5023 ensure s that when both b ucks ar e in pwm mode, they operate out of phase, whereby the b uck 2 p fet starts conducting exactly half a clock period after the buck1 p fet starts conducting. short - circuit prot ection the buck s include frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below half the target output voltage, indicating the possi - bility of a hard short at the output, the switching frequen cy is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. soft start the buck s have an internal soft start function that ramps t he output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit each buck has p rotection circuitry to limit the amount of positive current flowing through the p fet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can f low from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a drop in input voltage , or with an increase in load current , the buck may reach a li mit where, even with the p fet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit, the buck transitions to a mode where the p fet switch stays on 100% of the time. when
ADP5023 data sheet rev. a | page 20 of 28 the input conditions change again and t he required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage . active pull - downs all regulators have optional , factory - programmable, active pull - down resistors discharging the respective output capacitors when the regulators are disabled. the pull - down resistors are c onnected between voutx and agnd. active pull - downs are disabled when the regulators are turned on. the typical value of the pull - down resistor is 6 00 for the ldo and 75 for the b ucks. figure 46 show s the activation timings for the ac tive pull - down s during regulator activation and deactivation. ldo the ADP5023 contains one ldo with low quiescen t curren t and low dropout voltage , and provide s up to 3 0 0 ma of output curr ent. drawing a low 10 a quiescent current (typical) at no load makes the ldo ideal for battery - operated portable equipment. the ldo oper ates with an input voltage of 1.7 v to 5.5 v. the wide operating range makes th ese ldo suitable for cascading configurations where the ldo s upply voltage is provided from one of the buck regulators. the ldo output voltage is set th r ough external resistor divider s as shown in figure 48 for ldo . the output voltage can optionally be factory programmed to default values as indicated in the ordering guide section. in this even t, ra and rb are not needed , and fb3 must be connected to the top of the capacitor on vout3 . fb3 is 0.5 v. ldo fb3 ra rb vout3 vout3 vin3 c7 1f v out3 = v fb3 + 1 ra rb 09889-009 figure 48 . ldo external output voltage setting the ldo also provide s high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with only a small 1 f ceramic input and output capacitor.
data sheet ADP5023 rev. a | page 21 of 28 applications informa tion b u ck external component s election trade - offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in f igure 1 . feedback resistor s for the adjustable model , referring to figure 47, the total combined resistance for r1 and r2 is not to exceed 400 k ?. inductor the high switching frequency of the ADP5023 b ucks allows the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 h. suggested inductors are shown in table 8 . the peak - to - peak inductor current r ipple is calculated using the following equation: l f v v v v i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak curren t is calculated using the following equation: 2 ) ( ripple max load peak i i i + = inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance ( dcr ) . larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losse s are related to the magnetic permeability of the core mate rial. because the bucks are high switching frequency dc - to - dc converter s , shielded ferrite core material is recommended for its low core lo sses and low emi. output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. when choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. cer amic capacitors are manufactured with a variety of dielec - trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recom - mended for best performance. y5v and z5u dielectrics are not recommended for use with any dc - to - dc converter because of their poor temperature and dc bias characteris tics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu - lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the opera ting voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolera nce of the capacitor (tol) is assumed to be 10% and c out is 9.2 f at 1.8 v, as shown in figure 49. substituting these values in the equation yields c eff = 9.2 f (1 ? 0.15) (1 ? 0.1) = 7.0 f to guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0 1 2 3 4 5 6 dc bias vo lt age (v) ca p aci t ance (f) 09889-010 figure 49 . capacitance vs. voltage characteristic table 8 . suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18f n1r0 m00b 3.2 2.5 1.5 2300 54 taiyo yuden cbc3225t1r0mr 3.2 2.5 2.5 2000 71 coilcraft xfl4020 - 102me 4 .0 4 .0 2.1 5400 11 coilcraft xpl2010 - 102ml 1.9 2.0 1.0 3750 89 toko mdt2520 - cn 2.5 2.0 1.2 1350 85
ADP5023 data sheet rev. a | page 22 of 28 the peak - to - peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: ( ) out sw in out sw ripple ripple c l f v c f i v = 2 2 8 capacitors with lower equivalent series resistance (esr) are prefer able to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperat ure and dc bias effects, is a minimum of 7 f and a maximum of 40 f . the buck regulators require 10 f output capacitors to guaran - tee stability and response to rapid load variations and to transition in to and out of the pwm/psm modes. a list of suggested capaci - tors is shown in table 9 . in certain applications where one or both buck regulator powers a processor, the operating state is known because it is controlled by software. in this condition, the processor can drive the mode pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large load var iation when working in psm mode ( see figure 50) . input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v v v v i i ) ( ) ( ? to minimize su pply noise, place the input capacitor as close as possible to the vin x pin of the buck . as with the output capacitor, a low esr capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects, is a m inimum of 3 f and a maximum of 10 f. a list of suggested capacitors is shown in table 10. table 9 . suggested 10 ?f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3 table 10 . suggested 4.7 ?f capacitors vendor type m odel case size voltage rating (v) murata x5r grm188r60j475me19d 0402 6.3 taiyo yuden x5r jmk107bj475 0402 6.3 panasonic x5r ecj - 0eb0j475m 0402 6.3 table 11 . suggested 1.0 ?f capacitors vendor type model case size voltage rating (v) murata x5r grm155b30j105k 0402 6.3 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv - f 0402 10.0 vin1 vin3 en1 pwm psm/pwm 2.3v t o 5.5v sw1 fb1 r2 r1 vout1 pgnd1 mode c5 10f v out1 a t 800m a v out2 a t 800m a v out3 a t 300m a l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f a vin c fi l t 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v t o 5.5v on off on off en3 ldo (analog) ADP5023 housekeeping sw2 fb2 r4 r3 vout2 pgnd2 c6 10f l2 1h fb3 r6 r5 vout3 c7 1f 09889-248 figure 50 . processor system power management with psm/pwm control
data sheet ADP5023 rev. a | page 23 of 28 ldo e xternal c omponent s election feedback resistor s for the adjustable model , the maximum v alue of rb is not to exceed 200 k ? (see figure 48) . output capacitor the ADP5023 ldo is designed for operation with small, space - saving ceramic capacitors, but functions with most commonly used capacit ors as long as care is taken with the esr value. the esr of the out put capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 ? or less is recommended to ensure stability of the ADP5023 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ADP5023 to large changes in load current. input bypass capacitor connecting a 1 f capacitor from vin3 to ground reduces the cir cuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedance are encountered. if greate r than 1 f of output capacitance is required, increase the input capacitor to match it. input and output capacitor properties use any good quality ceramic capacitors with the ADP5023 as long as they meet the m inimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capaci tance over the necessary tempera - ture range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best perfor - mance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the ca pacitor size and voltage rating . in general, a capacitor in a larger package or higher voltag e rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera - ture range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 dc bias vo lt age (v) ca p aci t ance (f) 09889-012 figure 51 . capacitance vs. voltage characteristic use the following equation to determine the worst - case capa - citance accounting for capacitor variation over temperature, component tolerance, and vol tage. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient ( tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10% and c bias is 0. 85 f at 1.8 v as shown in figure 51. substituting these val ues into the following equation: c eff = 0. 85 f (1 ? 0.1 5) (1 ? 0.1) = 0. 65 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the pe r formance of the ADP5023 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors are evaluated for each application.
ADP5023 data sheet rev. a | page 24 of 28 p cb layout guidelines poor layout can affect ADP5023 performance, causing electro - magnetic interference (emi) and electromag netic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stabilit y. a good layout is implemented using the following guidelines . also, refer to user guide ug - 271. ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components ca rry high switching frequencies, and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal di ssipation. ? use a ground plane with several vias connecting to the com ponent side ground to fur ther reduce noise interference on sensitive circuit nodes. ? connect vin1, vin2 , and avin together close to the ic using short tracks.
data sheet ADP5023 rev. a | page 25 of 28 typical application s chema tic s vin1 vin3 en1 pwm psm/pwm 2.3v to 5.5v sw1 fb1 vout1 pgnd1 mode c5 10f v out1 at 800ma v out2 at 800ma v out3 at 300ma l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f avin c filt 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v to 5.5v on off on off en3 ldo (analog) ADP5023 housekeeping sw2 fb2 vout2 pgnd2 c6 10f l2 1h fb3 vout3 c7 1f 09889-150 figure 52 . ADP5023 fixed output voltages with enable pins vin1 vin3 en1 pwm psm/pwm 2.3v t o 5.5v sw1 fb1 r2 r1 vout1 pgnd1 mode c5 10f v out1 a t 800m a v out2 a t 800m a v out3 a t 300m a l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f a vin c fi l t 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v t o 5.5v on off on off en3 ldo (analog) ADP5023 housekeeping sw2 fb2 r4 r3 vout2 pgnd2 c6 10f l2 1h fb3 r6 r5 vout3 c7 1f 09889-151 figure 53 . ADP5023 adjustable output voltages with enable pins
ADP5023 data sheet rev. a | page 26 of 28 bill of materials table 12. reference value part number vendor package or dimension (mm) c avin 0.1 f, x5r, 6.3 v jmk105bj104mv -f taiyo - yuden 0402 c3, c7 1 f, x5r, 6.3 v lmk105bj105mv -f taiyo - yuden 0402 c1, c2 4.7 f, x5r, 6.3 v ecj - 0eb0j475m panasonic - ecg 0402 c5, c6 10 f, x5r, 6.3 v jmk107bj106ma - t taiyo - yuden 0603 l1, l2 1 h, 0.18 , 850 ma brc1608t1r0m taiyo - yuden 0603 1 h, 0.085 , 1400 ma lqm2mpn1r0ng0b murata 2.0 1.6 0.9 1 h, 0.059 , 900 ma epl2014 - 102ml coilcraft 2.0 2.0 1.4 1 h, 0.086 , 1350 ma mdt2520 - cn toko 2.5 2.0 1.2 ic1 three - regulator micro pmu a dp50 23 analog devices 24- lead lfcsp
data sheet ADP5023 rev. a | page 27 of 28 outline d imensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant t o jedec standards mo-220-wggd-8. 072809 a b o t t o m v i e w t o p v i e w e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 1 2 4 7 1 2 1 3 1 8 1 9 6 for proper conne ction of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 2.20 2.10 sq 2.00 figure 54 . 24 - lea d lead frame chip scale package [ l f csp _wq ] 4 mm 4 mm body, very very thin quad (cp - 24 - 10) dimensions shown in millimeters ordering guide model 1 tempe rature range output voltage 2 uvlo 3 active pull - down 4 package description package option adp50 23 acpz -r7 ? 40c to +125c adjustable low enabled on buck channels 24- lead frame chip scale package [lfcsp_wq] cp -24-10 adp50 23 acpz -1 -r7 ? 40c to +125c vout1 = 1.2 v vout2 = 3.3 v vout3 = 2.8 v low enabled on buck channels 24- lead frame chip scale package [lfcsp_wq ] cp -24-10 adp50 23 cp - evalz evaluation board for adp50 23 acpz -r7 1 z = rohs compliant par t. 2 for additional options, contact a local sales or distribution representative . additional options available are: buck1 and buck2: 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.3 v, 2.0 v, 1.8 v, 1.6 v, 1.5 v , 1.4 v, 1.3 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v or adjustable. ldo: 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.25 v, 2 v, 1.8 v, 1.7 v, 1.6 v, 1.5 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v, 0.8 v or adjustable. 3 uvlo: low or high . 4 buck1, buck2, ldo: active pull - down resistor is pr ogrammable to be either enabled or disabled.
ADP5023 data sheet rev. a | page 28 of 28 notes ?2011-2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09889-0-1/12(a)

▲Up To Search▲

Price & Availability of ADP5023

	To Download ADP5023 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .